1. Field of the Invention
The invention relates generally to the semiconductor power devices. More particularly, this invention relates to an improved and novel manufacturing process and device configuration for controlling the depth of polysilicon etch-back from a trench wherein one of the applications is to provide the shielded trench gates having precisely controllable depth below the silicon top surface such that the reduction of gate to drain capacitance can be accurately achieved.
2. Description of the Prior Art
Conventional technologies for reducing the gate to drain capacitance Cgd in a DMOS device are still confronted with technical limitations and difficulties. Specifically, trenched DMOS devices are configured with trenched gates wherein large capacitance (Cgd) between gate and drain limits the device switching speed. The capacitance is mainly generated from the electrical field coupling between the bottom of the trenched gate and the drain. In order to reduce the gate to drain capacitance, an improved Shielded Gate Trench (SGT) structure is introduced at the bottom of the trenched gate to shield the trenched gates from the drain. The design concept of a SGT structure is to link the bottom of the trench to the source such that the trenched gates are shielded from the drain located at the bottom of the substrate as that shown in FIG. 1. A reduction of gate to drain capacitance to about half of the original Cgd value can be achieved by implementing the SGT structure in the bottom of the trenched gates. The switching speed and switching efficiency of the DMOS devices implemented with the SGT structure at the bottom of the trenched gates are therefore greatly improved.
As disclosed in U.S. Pat. Nos. 5,998,833 and 5,126,807, the shield gate trench (SGT) MOSFET is demonstrated as a promising solution in high speed switching applications with the SGT function as a floating gate in the lower part of the trench or fix to a source voltage. However, the challenge of the process is to control the depth of the floating gate that avoids the malfunction of the MOSFET. For this reason, great cares are required in the manufacturing processes in order to achieve the Cgd improvement by implementing such architecture. A particular time-etch of the polysilicon from the bottom of the gate trenches must be accurately controlled. FIG. 1A shows a DMOS device supported on a substrate 10. The substrate 10 includes an epitaxial layer 15 that has a trenched gate 20. The trenched gate 20 includes a polysilicon gate filled in the trenches with gate insulation layer 45. Under the trenched gate 20, a separated shielded gate trench (SGT) structure 30 is formed that includes polysilicon filling the trench bottom space separated from the trenched gate 20 with an insulation layer 40. The DMOS device further includes the body regions and source regions 50 and 60 as the standard DMOS devices. The depth of the bottom of the trenched gate, i.e., D as shown in FIG. 1A, is dependent on the etch rate of the polysilicon from the top portion of the trench when forming the SGT structure 30. A carefully controlled time etch is carried out to control the depth D.
FIGS. 1B and 1C show the processing steps to form the STG at the lower part of the trench gate. In FIG. 1B, the trench is filled with polysilicon. In FIG. 1C, a controlled polysilicon etch process is carried out to remove the polysilicon from the top of the trench until a designated depth, e.g., D is removed. However, the depth of the trench bottom D cannot be accurately controlled due to the variations of the etch speed of the polysilicon from the top portion of the trenches. This process is inherently difficult to control because this is not an end point etch. Thus leave the time control etch the only option. However, the etching rate highly depends on the trench sizes in active area and overall loading effect. Therefore, the etch time is different from product to product. As the feature size shrinking becomes technique trends nowadays, the floating gate etch control will become more challenging and tedious task.
As described above, even with accurate time control of an etch process, the depth of the polysilicon gate relative to the top surface of the silicon substrate cannot be controlled with sufficient accuracy. Variations of the gate depth are difficult to control because of the facts that in addition to the length of etch time, the speed of polysilicon etch at the bottom of the trenched gates is also dependent on several parameters that can all cause variations of the depth of the trenched gates. However, the variations of the depth of the gate bottom directly impact the device performance including the gate to drain capacitance. The variations of the gate depth further impact the difficulties in controlling the device channels. The reduction of the gate to drain capacitances cannot be fully realized unless special cares are implemented to control the etch speed of polysilicon from the trench bottom in order to control the depth of the trenched gates.
Therefore, a need still exists in the art of power semiconductor device design and manufacture to provide new manufacturing method and device configuration in forming the power devices such that the above discussed problems and limitations can be resolved.